This application claims the priority of Korean Patent Application No. 2003-50496, filed on Jul. 23, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor chip and a mount structure, and more particularly, to a liquid crystal display drive IC (LDI) chip and the mount structure in which the chip is connected to an external electronic device by a bump.
2. Description of the Related Art
A liquid crystal display (LCD) is a flat-panel display having the excellent characteristics of thinness, light-weight, and low power consumption. In addition, the LCD also has such characteristics of high resolution, high color display, and high definition.
As is well known, the LCD is made up of a liquid crystal panel (LCP) having liquid crystal injected between two substrates (an array and color filter substrate), a back light in a lower portion of the LCP, and a drive unit at an outer ring of the LCP to drive the LCP. The LCP consists of pixels in a matrix shape between two glass substrates with a switching device for controlling signals respectively supplied to the pixels, like a thin-film transistor.
The drive unit includes a printed circuit board (PCB), comprising hardware to generate control and data signals, and a liquid crystal display drive IC (LDI) which connects to the LCP and PCB to signal a LCP wire. Mount structures for an LDI chip include chip on glass (COG), tape carrier package (TCP), chip on film (COF), etc. LDI chip mounting requires a fine pitch connection, an easy connecting process, and high reliability to meet a trend in a complicated structure of the LDI chip, an increase in the number of pixels, and obtain high resolution. An exemplary technology for meeting this trend is a method of forming an Au bump and bonding a fine pad pitch.
FIGS. 1 through 4 show a manufacturing method of a conventional Au bump used in mounting a LDI chip.
FIG. 1 illustrates coating a chip in a wafer-state 1 with a passivation film 5 and covering an open Al pad 3 with polyimide and patterning to expose the Al pad 3.
FIG. 2 illustrates forming an under bump metallurgy (UBM) layer 9 by sputtering in an upper portion of the intermediate structure obtained in FIG. 1, and forming a photoresist pattern 11 having a hole A in a corresponding location to the Al pad 3 on the UBM layer 9.
A bump 13 is formed by filling the hole A with Au layers via Au electroplating as shown in FIG. 3, and photoresist pattern 11 is removed via stripping as illustrated in FIG. 4. Next, an etching process of the UBM layer 9 is performed so that the UBM layer 9 remains in a lower portion of the bump 13. The remaining UBM layer is indicated as 9a in FIG. 4.
The bump 13 is conventionally formed on the Al pad 3, thus exposing the passivation film 5 on the lower portion of the bump. The exposed passivation film 5 on the lower portion of the bump 13 makes it difficult to overcome step difference and, furthermore, causes the step difference in an upper portion of the bump 13. Additionally, the rough upper portion of the bump hampers the bonding process, and chip size is inevitably big due to the formation of the bump 13 on the Al pad 3. To simplify manufacturing, the size of bump 13 and the space between bumps 13 can be large. It is also difficult to embody the fine pad pitch since the Al pad 3 is disposed in a circumferential pad area separated from a cell (or circuit) area.
FIG. 5 displays a conventional redistribution bump 28. The upper portion of the bump 28 may be rough and an edge of the bump 28 may have protrusions as the bump 28 is formed by leaving the UBM layer 26 as a via for electrical connection in a bump formation location, and protecting a remaining area via the passivation film 27 after forming the redistribution metal wire 25. Reference numerals 21, 22, 23, and 24 indicate a chip in a wafer-state, an Al pad, and first and second passivation films, respectively.